1. Field of the Invention
The present invention relates to a signal processing apparatus that outputs a voltage signal corresponding to electric charges accumulated in a photodiode in a wide dynamic range, and also to a solid-state imaging device and a pixel signal generating method.
2. Description of the Related Art
A complementary metal oxide semiconductor (CMOS) image sensor, which is one type of solid-state imaging devices, resets a floating diffusion (FD) voltage to a pixel supply voltage at the time of reading a pixel signal. That is, because the CMOS image sensor has supply voltage dependency, if the pixel supply voltage decreases, the FD voltage also decreases. Further, a signal output to a vertical signal line is a signal obtained by detecting the FD voltage by an amplifier transistor. Therefore, if the FD voltage decreases, the voltage of an output signal to the vertical signal line also decreases. Accordingly, in a device including a CMOS image sensor, when it is attempted to realize reduction of power consumption, there is a problem that a saturated signal amount of a pixel cannot be output sufficiently.
Meanwhile, Japanese Patent Application Laid-Open No. 2005-86595 discloses a semiconductor device (a CMOS sensor) that attempts to solve the above problem and to realize reduction of power consumption and expansion of dynamic range. According to this semiconductor device, a period during which a reset pulse is being turned on at the time of resetting an FD is set shorter than usual (sufficiently shortened with respect to a transit time of a vertical signal line), to increase a preset voltage to the FD, thereby realizing reduction of power consumption and expansion of dynamic range.
However, in the semiconductor device of Japanese Patent Application Laid-Open No. 2005-86595, because an increase width of the preset voltage depends on its control timing, there is a problem that it is difficult to control the voltage at an optimum timing at which a sufficient effect can be obtained. Further, in a case of a CMOS sensor having a large number of pixels, a waveform of the reset pulse becomes dull due to a resistor-capacitor (RC) time constant. Therefore, to reset the FD, the pulse width needs to be widened, and when the pulse width is widened, its voltage rise effect is lessened. Accordingly, it is difficult to apply the technique described in Japanese Patent Application Laid-Open No. 2005-86595 to a CMOS sensor having a large number of pixels. In addition, because a voltage rise effect varies according to a load capacity of a vertical signal line, when the load capacity of the vertical signal line is small, the transit time of the vertical signal line is also shortened, and therefore a sufficient voltage rise effect cannot be obtained.